?2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6920MR " Rev. 1.0.8
9
Electrical Characteristics (Continued)
V
DD
=15 V and T
A
=25癈 unless otherwise noted.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
PFC Current-Sense Section
V
CSPFC
Threshold Voltage for Peak Current
Cycle-by-Cycle Limit
COMP
=5 V
0.77
0.82
0.87
V
t
PD
Propagation Delay
110
200
ns
t
BNK
Leading-Edge Blanking Time
110
180
250
ns
A
V
CSPFC Compensation Ratio for THD
0.90
0.95
1.00
V/V
PFC Output Section
V
Z
PFC Gate Output Clamping Voltage
DD
=25 V
14.0
15.5
17.0
V
V
OL
PFC Gate Output Voltage Low
DD
=15 V,
I
O
=100 mA
1.5
V
V
OH
PFC Gate Output Voltage High
DD
=15 V,
I
O
=100 mA
8
V
t
R
PFC Gate Output Rising Time
DD
=12 V, C
L
=3 nF,
0~80%
30
65
100
ns
t
F
PFC Gate Output Falling Time
DD
=12 V, C
L
=3 nF,
0~20%
30
50
70
ns
PFC Zero-Current Detection Section
V
Z D
In ut Threshold Volta e Risin Ed e
Z D
Increasin
1.9
2.1
2.3
V
V
ZCD-HYST
Threshold Voltage Hysteresis
ZCD
Decreasing
0.25
0.35
0.45
V
V
ZCD-HIGH
Upper Clamp Voltage
I
ZCD
=3 mA
8
10
V
V
ZCD-LOW
Lower Clamp Voltage
0.35
0.45
0.55
V
V
ZCD-SSC
Starting Source Current Threshold
Voltage
0.70
0.90
1.10
V
t
DELAY
Maximum Delay from ZCD to Output
Turn-On
COMP
=5 V,
= kHz
100
200
ns
t
RESTART-PFC
Restart Time
300
500
700
祍
t
INHIB
Inhibit Time (Maximum Switching
Frequency Limit)
COMP
=5 V
1.5
2.5
3.5
祍
V
ZCD-DIS
PFC Enable / Disable Function
Threshold Voltage
0.15
0.20
0.25
V
t
ZCD-DIS
PFC Enable / Disable Function
Debounce Time
ZCD
=100 mV
100
150
200
祍
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